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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity bcd_to_7seg is
    Port ( bcd : in  unsigned (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (6 downto 0));
end bcd_to_7seg;
 
architecture default of bcd_to_7seg is
begin
  with bcd select
    seg <= "1000000" when "0000",
           "1111001" when "0001",
           "0100100" when "0010",
           "0110000" when "0011",
           "0011001" when "0100",
           "0010010" when "0101",
           "0000010" when "0110",
           "1111000" when "0111",
           "0000000" when "1000",
           "0010000" when "1001",
           "-------" when others;
end default;