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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity sseg_test is
    Port ( clk : in  STD_LOGIC;
           sw : in  STD_LOGIC_VECTOR (7 downto 0);
           an : out  STD_LOGIC_VECTOR (3 downto 0);
           seg : out  STD_LOGIC_VECTOR (6 downto 0);
           dp : out  STD_LOGIC);
end sseg_test;
 
architecture default of sseg_test is
  signal inverse: unsigned(7 downto 0);
  signal en: std_logic_vector(3 downto 0);
  signal v: std_logic_vector(3 downto 0);
begin
  inverse <= not unsigned(sw);
 
  display_multiplexer: entity timemux_4x4
                       port map( clk => clk, 
                                 reset => '0',
                                 d0 => sw(3 downto 0),
                                 d1 => sw(7 downto 4),
                                 d2 => std_logic_vector(inverse(3 downto 0)),
                                 d3 => std_logic_vector(inverse(7 downto 4)),
                                 lo_en => en,
                                 q => v);
 
  seven_segment_decoder: entity bcd_to_7seg port map(bcd => unsigned(v), seg => seg);
  dp <= en(2);
  an <= en;
end default;