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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity timemux_4x4 is
    Port ( clk : in  STD_LOGIC;
           reset : in std_logic;
           d0 : in  STD_LOGIC_VECTOR (3 downto 0);
           d1 : in  STD_LOGIC_VECTOR (3 downto 0);
           d2 : in  STD_LOGIC_VECTOR (3 downto 0);
           d3 : in  STD_LOGIC_VECTOR (3 downto 0);
           lo_en : out  STD_LOGIC_VECTOR (3 downto 0);
           q : out  STD_LOGIC_VECTOR (3 downto 0));
end timemux_4x4;
 
architecture default of timemux_4x4 is
  constant DIVIDER_SHIFT: natural := 16;
  signal combined: unsigned(DIVIDER_SHIFT+1 downto 0);
  signal counter: unsigned(1 downto 0);
begin
  process (clk, reset)
  begin
    if reset = '1' then
      combined <= (others => '0');
    elsif rising_edge(clk) then
      combined <= combined + 1;
    end if;
  end process;
 
  counter <= combined(combined'high downto combined'high+1-counter'length);
 
  process (counter, d0, d1, d2, d3)
  begin
    case counter is
      when "00" =>
        lo_en <= "1110";
        q <= d0;
      when "01" =>
        lo_en <= "1101";
        q <= d1;
      when "10" =>
        lo_en <= "1011";
        q <= d2;
      when "11" =>
        lo_en <= "0111";
        q <= d3;
      when others =>
        lo_en <= "----";
        q <= "----";
    end case;
  end process;
end default;